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74abt16374b 16-bit d-type flip-flop; positive-edge trigger (3-state) product data supersedes data of 2004 mar 01 2004 mar 08 integrated circuits
philips semiconductors product data 74abt16374b 16-bit d-type flip-flop; positive-edge trigger (3-state) 2 2004 mar 08 description the 74abt16374b high-performance bicmos device combines low static and dynamic power dissipation with high speed and high output drive. the 74abt16374b has two 8-bit, edge triggered registers, with each register coupled to eight 3-state output buffers. the two sections of each register are controlled independently by the clock (ncp) and output enable (noe ) control gates. each register is fully edge triggered. the state of each d input, one set-up time before the low-to-high clock transition, is transferred to the corresponding flip-flop's q output. the 3-state output buffers are designed to drive heavily loaded 3-state buses, mos memories, or mos microprocessors. each active-low output enable (noe ) controls all eight 3-state buffers for its register independent of the clock operation. when noe is low, the stored data appears at the outputs for that register. when noe is high, the outputs for that register are in the high-impedance aoffo state, which means they will neither drive nor load the bus. features ? two 8-bit positive edge triggered registers ? live insertion/extraction permitted ? power-up 3-state ? power-up reset ? multiple v cc and gnd pins minimize switching noise ? 3-state output buffers ? output capability: +64 ma/32 ma ? latch-up protection exceeds 500ma per jedec std 17 ? esd protection exceeds 2000 v per mil std 883 method 3015 and 200 v per machine model quick reference data symbol parameter conditions t amb = 25 c; gnd = 0 v typical unit t plh t phl propagation delay ncp to nqx c l = 50 pf; v cc = 5 v 2.6 2.2 ns c in input capacitance v i = 0 v or v cc 4 pf c out output capacitance v o = 0v or v cc ; 3-state 7 pf i ccz quiescent su pp ly current outputs disabled; v cc = 5.5 v 500 m a i ccl q u iescent s u ppl y c u rrent outputs low; v cc = 5.5 v 8 ma ordering information t amb = 40 c to +85 c type number package name description version 74ABT16374BB qfp52 plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 10 2.0 mm sot379-1 74abt16374bdgg tssop48 plastic thin shrink small outline package; 48 leads; body width 6.1 mm sot362-1 74abt16374bdl ssop48 plastic shrink small outline package; 48 leads; body width 7.5 mm sot370-1
philips semiconductors product data 74abt16374b 16-bit d-type flip-flop; positive-edge trigger (3-state) 2004 mar 08 3 pin configuration tssop48 and ssop48 pinning 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1oe 1q0 1q1 gnd 1q2 1q3 1q4 1q5 gnd 1q6 1q7 2q0 2q1 gnd 2q3 v cc 2q4 v cc 2q2 2q5 gnd 2q7 2oe 2q6 1cp 1d0 1d1 gnd 1d2 1d3 1d4 1d5 gnd 1d6 1d7 2d0 2d1 gnd 2d3 v cc 2d4 v cc 2d2 2d5 gnd 2d7 2cp 2d6 sa00326 qfp52 pinning 1 2 3 4 5 6 7 v cc 1q4 1q5 gnd 1q6 gnd 1q7 8 9 10 11 2q0 2q1 2q2 gnd 74ABT16374BB qfp52 12 13 2q3 v cc 2q4 sw02219 14 15 16 17 18 19 20 21 22 23 24 25 26 39 38 37 36 35 34 33 32 31 30 29 28 27 2q5 gnd 2q6 2q7 2oe gnd 2cp 2d7 2d6 gnd 2d5 2d4 v cc 1d4 1d5 gnd 1d6 gnd 1d7 2d0 2d1 2d2 gnd 2d3 v cc 52 51 50 49 48 47 46 45 44 43 42 41 40 1q3 1q2 gnd 1q1 1q0 1oe gnd 1cp 1d0 1d1 gnd 1d2 1d3 pin description pin number symbol function tssop and ssop qfp52 symbol function 47, 46, 44, 43, 41, 40, 38, 37 36, 35, 33, 32, 30, 29, 27, 26 44, 43, 41, 40, 38, 37, 35, 34 32, 31, 29, 28, 26, 25, 23, 22 1d0 1d7 2d0 2d7 data inputs 2, 3, 5, 6, 8, 9, 11, 12 13, 14, 16, 17, 19, 20, 22, 23 48, 49, 51, 52, 2, 3, 5, 6 8, 9, 11, 12, 14, 15, 17, 18 1q0 1q7 2q0 2q7 data outputs 1, 24 47, 19 1oe , 2oe output enable inputs (active-low) 48, 25 45, 21 1cp, 2cp clock pulse inputs (active rising edge) 4, 10, 15, 21, 28, 34, 39, 45 4, 7, 10, 16, 20, 24, 30, 33, 36, 42, 46, 50 gnd ground (0 v) 7, 18, 31, 42 1, 13, 27, 39 v cc positive supply voltage
philips semiconductors product data 74abt16374b 16-bit d-type flip-flop; positive-edge trigger (3-state) 2004 mar 08 4 logic symbol 3 2 1q0 1q1 1q2 6 5 1q3 47 46 44 43 1d0 1d1 1d2 1d3 48 1 9 8 1q4 1q5 1q6 12 11 1q7 41 40 38 37 1d4 1d5 1d6 1d7 1cp 1oe 14 13 17 16 36 35 33 32 25 24 20 19 23 22 30 29 27 26 2q0 2q1 2q2 2q3 2d0 2d21 2d2 2d3 2q4 2q5 2q6 2q7 2d4 2d5 2d6 2d7 2cp 2oe sh00078 logic symbol (ieee/iec) 1en 1 ? c1 2en c2 1d 2 ? 2d sh00077 1 48 24 25 47 46 44 43 41 40 38 37 36 35 33 32 30 29 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 26 27 1oe 1cp 2oe 2cp 1d0 1d1 1d2 1d3 1d4 1d5 1d6 1d7 2d0 2d1 2d2 2d3 2d4 2d5 2d6 2d7 1q0 1q1 1q2 1q3 1q4 1q5 1q6 1q7 2q0 2q1 2q2 2q3 2q4 2q5 2q6 2q7 logic diagram cp q d nd0 nq0 cp q d nd1 cp q d nd2 cp q d nd3 cp q d nd4 cp q d nd5 cp q d nd6 cp q d nd7 nq1 nq2 nq3 nq4 nq5 nq6 nq7 ncp noe sa00327 function table inputs internal outputs operating mode noe ncp ndx register nq0 nq7 operating mode l l l h l h l h load and read register l x nc nc hold h h x ndx nc ndx z z disable outputs h = high voltage level h = hiigh voltage level one set-up time prior to the high-to-low e transition l = low voltage level l = low voltage level one set-up time prior to the high-to-low e transition nc= no change x = don't care z = high-impedance aoffo state = low-to-high clock transition = not a low-to-high clock transition
philips semiconductors product data 74abt16374b 16-bit d-type flip-flop; positive-edge trigger (3-state) 2004 mar 08 5 absolute maximum ratings 1, 2 symbol parameter conditions rating unit v cc dc supply voltage 0.5 to +7.0 v i ik dc input diode current v i < 0 v 18 ma v i dc input voltage 3 1.2 to +7.0 v i ok dc output diode current v o < 0 v 50 ma v out dc output voltage 3 output in off or high state 0.5 to +5.5 v i o dc out p ut current output in low state 128 ma i out dc o u tp u t c u rrent output in high state 64 ma t stg storage temperature range 65 to 150 c notes: 1. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditionso is not implied. exposur e to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create ju nction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not excee d 150 c. 3. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. recommended operating conditions symbol parameter limits unit symbol parameter min max unit v cc dc supply voltage 4.5 5.5 v v i input voltage 0 v cc v v ih high-level input voltage 2.0 v v il low-level input voltage 0.8 v i oh high-level output current 32 ma i ol low-level output current 64 ma d t/ d v input transition rise or fall rate 0 10 ns/v t amb operating free-air temperature range 40 +85 c
philips semiconductors product data 74abt16374b 16-bit d-type flip-flop; positive-edge trigger (3-state) 2004 mar 08 6 dc electrical characteristics limits symbol parameter test conditions t amb = +25 c t amb = 40 c to +85 c unit min typ max min max v ik input clamp voltage v cc = 4.5 v; i ik = 18 ma 0.9 1.2 1.2 v v cc = 4.5 v; i oh = 3 ma; v i = v il or v ih 2.5 2.9 2.5 v v oh high-level output voltage v cc = 5.0 v; i oh = 3 ma; v i = v il or v ih 3.0 3.4 3.0 v v cc = 4.5 v; i oh = 32 ma; v i = v il or v ih 2.0 2.4 2.0 v v ol low-level output voltage v cc = 4.5 v; i ol = 64 ma; v i = v il or v ih 0.42 0.55 0.55 v v rst power-up output voltage 3 v cc = 5.5 v; i o = 1 ma; v i = gnd or v cc 0.13 0.55 0.55 v i i input leakage current v cc = 5.5 v; v i = v cc or gnd 0.01 1 1 m a i off power-off leakage current v cc = 0.0 v; v o or v i 4.5 v 5.0 100 100 m a i pu/pd power-up/down 3-state output current 4 v cc = 2.1 v; v o = 0.5 v; v i = gnd or v cc ; v oe = gnd 5.0 50 50 m a i ozh 3-state output high current v cc = 5.5 v; v o = 2.7 v; v i = v il or v ih 0.5 10 10 m a i ozl 3-state output low current v cc = 5.5 v; v o = 0.5 v; v i = v il or v ih 0.5 10 10 m a i cex output high leakage current v cc = 5.5 v; v o = 5.5 v; v i = gnd or v cc 5.0 50 50 m a i o output current 1 v cc = 5.5 v; v o = 2.5 v 50 70 180 50 180 ma i cch v cc = 5.5 v; outputs high; v i = gnd or v cc 0.5 2 2 ma i ccl quiescent supply current v cc = 5.5 v; outputs low; v i = gnd or v cc 8 19 19 ma i ccz v cc = 5.5 v; outputs 3-state; v i = gnd or v cc 0.5 2 2 ma d i cc additional supply current per input pin 2 v cc = 5.5 v; one input at 3.4 v, other inputs at v cc or gnd 5 100 100 m a notes: 1. not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. this is the increase in supply current for each input at 3.4 v. 3. for valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. this parameter is valid for any v cc between 0 v and 2.1 v with a transition time of up to 10 msec. from v cc = 2.1 v to v cc = 5 v 10% a transition time of up to 100 m sec is permitted. 5. unused pins at v cc or gnd. ac characteristics gnd = 0 v, t r = t f = 2.5 ns, c l = 50 pf, r l = 500 w limits symbol parameter waveform t amb = +25 c v cc = +5.0 v t amb = 40 to +85 c v cc = +5.0v 0.5 v unit min typ max min max f max maximum clock frequency 1 180 260 mhz t plh t phl propagation delay ncp to nqx 1 1.7 1.4 2.6 2.2 4.0 3.4 1.7 1.4 4.7 3.9 ns t pzh t pzl output enable time to high and low level 3 4 1.3 1.3 2.4 2.3 3.7 3.4 1.3 1.3 4.7 4.6 ns t phz t plz output disable time from high and low level 3 4 1.9 1.7 3.1 2.6 4.6 4.0 1.9 1.7 5.5 4.4 ns
philips semiconductors product data 74abt16374b 16-bit d-type flip-flop; positive-edge trigger (3-state) 2004 mar 08 7 ac set-up requirements gnd = 0 v, t r = t f = 2.5 ns, c l = 50 pf, r l = 500 w limits symbol parameter waveform t amb = +25 c v cc = +5.0 v t amb = 40 to +85 c v cc = +5.0 v 0.5 v unit min typ min t s (h) t s (l) set-up time, high or low ndx to ncp 2 1.0 1.0 0.3 0.1 1.0 1.0 ns t h (h) t h (l) hold time, high or low ndx to ncp 2 1.0 1.0 0.1 0.3 1.0 1.0 ns t w (h) t w (l) ncp pulse width high or low 1 2.8 2.8 1.2 1.5 2.8 2.8 ns ac waveforms v m = 1.5v, v in = gnd to 3.0v vm vm vm vm vm 1/f max t w (h) t w (l) t phl t plh ncp nqx sa00328 waveform 1. propagation delay, clock input to output, clock pulse width, and maximum clock frequency v m ndx v m v m v m v m v m ncp t s (h) t h (h) t s (l) t h (l) note: the shaded areas indicate when the input is permitted to change for predictable output performance. sa00329 waveform 2. data set-up and hold times oe v m t pzh t phz 0v nqx v m v m sh00079 v oh v oh 0.3v waveform 3. 3-state output enable time to high level and output disable time from high level oe t pzl t plz nqx v m v m v m sh00080 v ol v ol + 0.3v waveform 4. 3-state output enable time to low level and output disable time from low level
philips semiconductors product data 74abt16374b 16-bit d-type flip-flop; positive-edge trigger (3-state) 2004 mar 08 8 test circuit and waveform pulse generator r t v in d.u.t. v out r l v cc r l 7.0 v test circuit for 3-state outputs v m v m t w amp (v) negative pulse 10% 10% 90% 90% 0 v v m v m t w amp (v) positive pulse 90% 90% 10% 10% 0 v t thl (t f ) t tlh (t r )t thl (t f ) t tlh (t r ) v m = 1.5 v input pulse definition definitions r l = load resistor; see ac characteristics for value. c l = load capacitance includes jig and probe capacitance; see ac characteristics for value. r t = termination resistance should be equal to z out of pulse generators. input pulse requirements family amplitude rep. rate t w t r t f 74abt 3.0 v 1 mhz 500 ns 2.5 ns 2.5 ns switch position test switch t plz closed t pzl closed all other open sa00654 c l
philips semiconductors product data 74abt16374b 16-bit d-type flip-flop; positive-edge trigger (3-state) 2004 mar 08 9 ssop48: plastic shrink small outline package; 48 leads; body width 7.5 mm sot370-1
philips semiconductors product data 74abt16374b 16-bit d-type flip-flop; positive-edge trigger (3-state) 2004 mar 08 10 tssop48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm sot362-1
philips semiconductors product data 74abt16374b 16-bit d-type flip-flop; positive-edge trigger (3-state) 2004 mar 08 11 qfp52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm sot379-1
philips semiconductors product data 74abt16374b 16-bit d-type flip-flop; positive-edge trigger (3-state) 2004 mar 08 12 revision history rev date description _4 20040308 product data (9397 750 13014). supersedes data of 2004 mar 01 (9397 750 12988). modifications: ? add type number 74ABT16374BB, qfp52 pin configuration, and sot379-1 package outline. _3 20040301 product data (9397 750 12988); 853-1752 ecn 01a15430 of 27 january 2004. replaces data sheet 74abt_h16374b_2 of 1998 feb 27 (9397 750 03496). _2 19980227 product specification (9397 750 03496); ecn 853-1752 19027 of 27 february 1998. supersedes data of 1995 sep 28. _1 19950928
philips semiconductors product data 74abt16374b 16-bit d-type flip-flop; positive-edge trigger (3-state) 2004 mar 08 13 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed i nformation see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the l imiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any o ther conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affec t device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors ma ke no representation or warranty that such applications will be suitable for the specified use without further testing or modificatio n. disclaimers life support e these products are not designed for use in life support appliances, devices, or systems where malfunction of these products ca n reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applica tions do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes in the productseincluding circuits, standard cells, and/or softwaree described or contained herein in order to improve design and/or performance. when the product is in full production (status `production') , relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for th e use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranti es that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2004 all rights reserved. printed in u.s.a. date of release: 03-04 document order number: 9397 750 13014

data sheet status [1] objective data preliminary data product data product status [2] [3] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change notification (cpcn). data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level i ii iii

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